Memory cells of dynamic random access memories (DRAMs) are usually provided with a respective storage capacitor for storing electrical charge and a selection transistor for addressing the storage capacitor. In this case, a lower limit results for a channel length of the selection transistor, below which lower limit the insulation properties of the selection transistor are inadequate in the turned-off, non-addressed state of the memory cell. The lower limit for an effective channel length Leff limits the scalability of conventional planar transistor cells (PTCs) with a selection transistor oriented horizontally with respect to a substrate surface of a semiconductor substrate.
The functionality of a memory cell is furthermore determined by the resistance of the selection transistor in the turned-on state given addressing of the memory cell. With advancing miniaturization of the structures, an effective channel width Weff of the selection transistor is being increasingly reduced and the charging/discharging current Ion of the memory cell is disadvantageously limited.
Therefore, fin field-effect transistors (FinFETs) are known, as are described for example in “Fabrication of Body-Tied FinFETs (omega MOSFETs) using Bulk Si Wafers,” Park et al.; in “2003 Symposium on VLSI Technology Digest of Technical Papers.” Between two source/drain regions of a transistor cell that are arranged in planar fashion, a semiconductor substrate is etched back by a recess step and a fin formed by the semiconductor substrate is shaped between the two source/drain regions in the process. A gate electrode structure envelops the fin from at least two sides. The effective channel length Leff is determined by the length of the fin in accordance with a minimum feature size F governed by the production technology. The effective channel width Weff is determined from the height of the fin, or the depth to which the recess step is carried out.
The effective channel length Leff is linked to the minimum feature size F and limits the scaling potential of the finFET with regard to the leakage current or the insulator properties in the off state. The switching threshold of the finFET depends greatly on production parameters. The fabrication of a fin field-effect transistor as selection transistor of a memory cell with a hole trench capacitor proves to be complex.
Arrangements with vertical transistor cells (VTCs) are known for memory cells with a hole trench capacitor. The source/drain regions of the selection transistor are essentially arranged vertically one above the other in the semiconductor substrate. A channel controlled by a gate electrode of the selection transistor is formed perpendicular to the cell array plane or substrate surface of the semiconductor substrate. The minimum channel width Weff results in accordance with the minimum feature size F. The channel length Leff is dependent on the depth at which the lower source/drain region or a lower edge of the gate electrode is formed.
Disadvantages of the vertical transistor cell are the difficult integration in memory cells having stacked capacitors, the increase in the aspect ratio of a hole trench for forming the memory cell in the case of integration in memory cells having hole trench capacitors, the restricted switch-on/switch-off current Ion and also the parasitic action of the gate electrode of a selection transistor on adjacent memory cells.
A vertical memory cell with a vertical transistor structure in which the gate electrode completely encloses a body region arranged between the two source/drain regions is described in “Fully Depleted Surrounding Gate Transistor (SGT) for 70 nm DRAM and Beyond”; Goebel et al. A fin is formed by etching back a semiconductor substrate. A first source/drain region is formed by outdiffusion from an adjacent structure in the base region of the fin. A second source/drain region is provided at the upper edge of the fin. The gate electrode is arranged along the four sidewalls of the fin. The effective channel length Leff results from the depth of etching back for the fin. The effective channel width Weff corresponds to the contour of the fin, at least one side length resulting in a manner dependent on the minimum feature size F. The total effective channel width correspondingly amounts to 2F to 3F. Like the vertical transistor cell, the transistor cell with a surrounding gate electrode, too, can only be integrated in a complex manner in memory cells having stacked capacitors. The high aspect ratios established in the course of processing and the resultant restrictions in the processing and with regard to the storage capacitor are furthermore disadvantageous.
A field-effect transistor with a curved channel is described in “The Breakthrough in Data Retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm Feature Size and Beyond”; Kim et al.; in “2003 Symposium on VLSI Technology Digest of Technical Papers.” The two source/drain regions of the field-effect transistor are arranged in a horizontal plane. The gate electrode is arranged in a recess trench introduced into the semiconductor substrate between the two source/drain regions of the transistor. The effective channel length Leff results from the distance between the two source/drain regions and also the depth to which the recess trench provided between the two source/drain regions is introduced into the semiconductor substrate. The effective channel width Weff corresponds to the minimum feature size F.
The continuing restriction of the effective channel width disadvantageously limits the switch-on/switch-off current.
In the case of integration of recess channel FETs in memory cells with a high packing density, the alignment of the gate electrodes with respect to the recess trenches proves to be complex, for instance if both are respectively patterned in the course of a photolithographic method. In contrast to finFET or SGT transistor cells, the active zone is not shielded from the adjacent memory cells by the gate electrode. A parasitic punchthrough of the potential of a gate electrode to the adjacent transistor cells occurs.
An arrangement for memory cells having hole trench capacitors and selection transistors having a gate electrode grooved into the semiconductor substrate (grooved gate) is described in U.S. Pat. No. 5,945,707 (Bronner et al.) and is explained below with reference to FIG. 1.
In accordance with FIG. 1, storage capacitors 6 are formed as hole trench capacitors 8 in a semiconductor substrate 1 below a substrate surface 10. A hole trench capacitor 8 comprises a storage electrode 61 arranged in the interior of a hole trench and a counterelectrode 63 formed as a doped zone in a section of the semiconductor substrate 1 that surrounds a lower section of the storage electrode 61. A capacitor dielectric 62 is provided between the storage electrode 61 and the counterelectrode 63. In an upper section of the hole trench capacitor 6, the storage electrode 61 is insulated from the semiconductor substrate 1 by a collar insulator structure 81.
An active zone 11 with two selection transistors 9, 9′ is formed by the semiconductor substrate 1 between in each case two adjacent capacitor structures 6. The source/drain regions 12, 13 of the selection transistors 9, 9′ are in each case doped sections of the active zone 11. A respective first source/drain region 12 adjoins the storage electrode 61 of a storage capacitor 6 in the region of a contact window 82. The second source/drain region 13 is connected via a bit contact 31 to a-data line 33 arranged above the substrate surface 10. The gate electrode 2 comprises a highly conductive section 2a. The gate electrodes of selection transistors that are adjacent in the direction perpendicular to the cross-sectional plane are connected to one another and form addressing lines. The addressing lines are enclosed by a gate stack insulator structure 95 and insulated from the data line 33 formed thereabove by an interlayer dielectric 41.
Between the two source/drain regions 12, 13 of the selection transistors 9, 9′, a recess trench 18 is introduced in each case from the substrate surface 10. The recess trench 18 is filled with the material of the gate electrode 2. A channel region 15 of the selection transistor 9, 9′ extends in the semiconductor substrate 1 along the sidewalls and the bottom of the recess trench 18. A gate dielectric 16 is provided between the gate electrode 2 and the semiconductor substrate 1. The recess trench 18 lengthens the effective channel length Leff with regard to a cell current 96 compared with a conventional planar transistor structure.
The patterning of the addressing lines is carried out in a manner aligned with the recess trenches 18 introduced beforehand and the patterning of the recess trenches 18 is carried out in a manner aligned with the hole trenches of the hole trench capacitors 8. The effective channel width Weff is disadvantageously predefined, in the direction perpendicular to the cross-sectional plane, by the distance with respect to the memory cells that are adjacent in this direction.